LTC2495CUHF#PBF【PDF 7/34 页】IC ADC 16BIT W/PGA 38-QFN

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LTC2495

2495fd

I2C INTERFACE

The LTC2495 communicates through an I2C interface. The

I2C interface is a 2-wire, open-drain interface supporting

multiple devices and multiple masters on a single bus. The

connected devices can only pull the data line (SDA) LOW

and can never drive it HIGH. SDA is required to be exter-

nally connected to the supply through a pull-up resistor.

When the data line is not being driven, it is HIGH. Data on

the I2C bus can be transferred at rates up to 100kbits/s in

the standard mode and up to 400kbits/s in the fast mode.

The VCC power should not be removed from the device

when the I2C bus is active to avoid loading the I2C bus

lines through the internal ESD protection diodes.

Each device on the I2C bus is recognized by a unique

address stored in that device and can operate either as a

transmitter or receiver, depending on the function of the

device. In addition to transmitters and receivers, devices

canalsobeconsideredasmastersorslaveswhenperform-

ing data transfers. A master is the device which initiates a

data transfer on the bus and generates the clock signals

to permit that transfer. Devices addressed by the master

are considered a slave.

The LTC2495 can only be addressed as a slave. Once

addressed, it can receive configuration bits (channel

selection, rejection mode, speed mode) or transmit the

last conversion result. The serial clock line, SCL, is always

an input to the LTC2495 and the serial data line SDA is

bidirectional. The device supports the standard mode and

the fast mode for data transfer speeds up to 400kbits/s.

Figure 2 shows the definition of the I2C timing.

The START and STOP Conditions

A START (S) condition is generated by transitioning SDA

from HIGH to LOW while SCL is HIGH. The bus is consid-

ered to be busy after the START condition. When the data

transfer is finished, a STOP (P) condition is generated by

transitioning SDA from LOW to HIGH while SCL is HIGH.

The bus is free after a STOP is generated. START and STOP

conditions are always generated by the master.

When the bus is in use, it stays busy if a repeated START

(Sr)isgeneratedinsteadofaSTOPcondition.Therepeated

START timing is functionally identical to the START and is

used for writing and reading from the device before the

initiation of a new conversion.

Data Transferring

After the START condition, the I2C bus is busy and data

transfer can begin between the master and the addressed

slave. Data is transferred over the bus in groups of nine

bits, one byte followed by one acknowledge (ACK) bit. The

master releases the SDA line during the ninth SCL clock

cycle. The slave device can issue an ACK by pulling SDA

LOW or issue a Not Acknowledge (NACK) by leaving the

SDA line high impedance (the external pull-up resistor will

hold the line HIGH). Change of data only occurs while the

clock line (SCL) is LOW.

Figure 2. Definition of Timing for Fast/Standard Mode Devices on the I2C Bus

applications inForMation

SDA

SCL

tHD(SDA)

tHD(DAT)

tSU(STA)

tSU(STO)

tSU(DAT)

tLOW

tHD(SDA)

tSP

tBUF

tHIGH

2495 F02

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